The prior art is replete with different techniques and processes for fabricating semiconductor devices such as MOS transistors. In accordance with one known fabrication technique, a MOS transistor is formed by creating a device structure on a semiconductor substrate, where the device structure includes a metal gate between two sidewall spacers. The area between the sidewall spacers and above the metal gate represents a gate opening. Gate straining is sometimes used to enhance the performance of MOS transistors—gate straining can be achieved by depositing strain-inducing material (such as compressive or tensile nitride) within the gate opening of the transistor and around the sidewall spacers.
Conductive vias that serve as source and drain interconnects can be formed in the strain-inducing material that surrounds the sidewall spacers. Conventional fabrication processes create the via holes after the strain-inducing material has been formed around the sidewall spacers. The creation of the via holes may cause the strain-inducing material to relax because the via holes result in a “free” boundary of the strain-inducing material. Relaxation of the strain-inducing material at this junction is undesirable because the beneficial strain-inducing characteristics of the material may be reduced or eliminated.